Next-Generation Memory Systems & Architecture

We are committed to advancing memory technologies and their associated architectural solutions. A key focus of our work is the development of holistic, disaggregated memory management solutions optimized for memory-centric computing paradigms. By addressing the challenges of distributed memory resources, we aim to design cohesive strategies that ensure efficient memory utilization and seamless data access across interconnected memory units. Additionally, we are innovating Compute Express Link (CXL)-based multi-tiered memory systems for memory-intensive applications. By integrating CXL technology, we aim to create tiered memory architectures that combine high-speed and high-capacity memory units to meet the demands of data-intensive workloads. Our research also enhances the CXL hardware architecture, focusing on accommodating hardware extensions. By designing flexible and extensible hardware frameworks, we seek to integrate novel memory technologies in a way that supports future scalability and innovation. Furthermore, we are exploring heterogeneous memory management, employing techniques such as memory deduplication and compression. These methods aim to optimize memory utilization by reducing redundancy and maximizing the effective capacity of memory resources. Our objective is to shape the future of memory systems and architectures by providing innovative solutions that empower memory-intensive computing, enable efficient data processing, and pave the way for more sophisticated and capable memory technologies.

Publications

  1. (Journal) NoHammer: Preventing Row Hammer With Last-Level Cache Management
  2. (Journal) T-CAT: Dynamic Cache Allocation for Tiered Memory Systems With Memory Interleaving
  3. (Conference) IDIO: Network-Driven, Inbound Network Data Orchestration on Server Processors
  4. (Conference) InnerSP: A Memory Efficient Sparse Matrix Multiplication Accelerator with Locality-Aware Inner Product Processing
  5. (Conference) GreenDIMM: OS-assisted DRAM Power Management for DRAM with a Sub-array Granularity Power-Down State
  6. (Journal) IDIO: Orchestrating Inbound Network Data on Server Processors
  7. (Patent) Method and Apparatus for detecting cache side channel attack using trusted execution environment
  8. (Patent) Device and Method for managing DRAM power
  9. (Journal) Exploiting OS-Level Memory Offlining for DRAM Power Management
  10. (Conference) Application-Transparent Near-Memory Processing Architecture with Memory Channel Network
  11. (Journal) Virtual Snooping Coherence for Multi-Core Virtualized Systems
  12. (Conference) vCache: Architectural support for transparent and isolated virtual LLCs in virtualized environments
  13. (Journal) vCache: Providing a Transparent View of the LLC in Virtualized Environments
  14. (Journal) Subspace Snooping: Exploiting Temporal Sharing Stability for Snoop Reduction
  15. (Conference) Virtual Snooping: Filtering Snoops in Virtualized Multi-cores
  16. (Conference) Subspace Snooping: Filtering Snoops with Operating System Support