Secure Computer Architecture

We secure modern processors and accelerators at the architectural level. Our work investigates microarchitectural side channels, transient execution, speculation, contention attacks, accelerator security, and memory integrity. We develop defenses that strengthen isolation without giving up the performance and programmability expected from contemporary systems.

Publications

  1. (Journal) ResidualEvil: Exploiting Post-Squash MSHR Contention for Transient Execution Attacks
  2. (Conference) SMOOTH: Hardware-Assisted Fine-Grained On-Chip Memory Management for Efficient On-Device LLM Inference
  3. (Conference) DarkStream: Exploiting Internal Throughput Contention in Data Streaming Accelerator for Timing Attacks
  4. (Conference) BrokenSleep: Remote Power Timing Attack Exploiting Processor Idle States
  5. (Journal) NoHammer: Preventing Row Hammer With Last-Level Cache Management
  6. (Conference) A Resiliency Coordinator Against Malicious Attacks for Cyber-Physical Systems
  7. (Journal) CPS 환경에 대한 Flush+Reload 캐시 부 채널 공격의 영향 및 Flush+Reload 캐시 부 채널 공격 탐지 기술
  8. (Patent) Method and apparatus for detecting cache side channel attack
  9. (Patent) Method and Apparatus for detecting cache side channel attack using trusted execution environment
  10. (Journal) Defending Against Flush+Reload Attack With DRAM Cache by Bypassing Shared SRAM Cache
  11. (Poster) Exploiting DRAM Cache for Defending Against Flush+Reload Attack
  12. (Patent) Method and System for securing a communication channel for the trusted execution environment