Yeji Jung
Ph.D. Student

Research Interests

  • Tiered memory system

Education

  • 2022 ~, M.S–Ph.D. Integrated Course, Dept. of Information and Communication Engineering, DGIST
  • 2021, M.S. Candidate, Dept. Information and Communication Engineering, DGIST
  • 2016~2021, Bachelor of Convergence engineering, School of Basic Science, DGIST

Publications

* Corresponding Author

[MICRO] Hwanjun Lee, Minho Kim, Yeji Jung, Seonmu Oh, Ki-Dong Kang, Seunghak Lee, and Daehoon Kim*.

Beyond Page Migration: Enhancing Tiered Memory Performance via Integrated Last-Level Cache Management and Page Migration

IEEE/ACM International Symposium on Microarchitecture (MICRO), 2025

[CAL] YunHyeong Jeon, Minwoo Jang, Hwanjun Lee, Yeji Jung, Jin Jung, Jonggeon Lee, Jinin So, and Daehoon Kim*.

RoPIM: A Processing-in-Memory Architecture for Accelerating Rotary Positional Embedding in Transformer Models

IEEE Computer Architecture Letters (CAL), 2025

[CAL] Hwanjun Lee, Seunghak Lee, Yeji Jung, and Daehoon Kim*.

T-CAT: Dynamic Cache Allocation for Tiered Memory Systems With Memory Interleaving

IEEE Computer Architecture Letters (CAL), 2023