HW/SW design to prevent the bit-flip by Row Hammering in DRAM

Seunghak Lee, Jaeha Kung, and Daehoon Kim*. Daegugyeongbuk Institute of Science and Technology (DGIST), 2024
DGIST Scholar Page
https://scholar.dgist.ac.kr/handle/20.500.11750/48034
DOI
10.22677/THESIS.200000723486

Abstract

(Under embargo until 2029-02-28)

Keywords

DRAM, Row Hammering, Integrity, Reliability, Memory Offlining.